Recently, various methods of increasing a surface area of a doped silicon or polycrystalline (poly) electrode plate capacitor to increase capacitance have been suggested. A method of forming hemispherical grain (HSG) poly on a lower conductive layer pattern of a capacitor is extensively utilized. Since a surface formed with HSG has a three dimensional alternating concave-convex structure, the effective surface area is increased and consequently capacitance is increased when the surface formed with HSG is utilized as a capacitor electrode.
There are two methods of forming HSG on a capacitor electrode. One method is a blanket HSG forming method whereby HSG is deposited over an entire surface which includes oxide insulator portions and lower conductive layer patterns of the capacitor electrode and then etching back the HSG down to the oxide insulator. The other method is a selective HSG forming method of forming the HSG only on the conductive layer patterns of the capacitor.
In the blanket HSG forming method, a problem encountered is that the practical capacitance is reduced when part of the HSG on the conductive layer patterns of the capacitor electrode portions are also etched during the HSG etch back step. As such, the blanket HSG forming method is not used as often as the selective HSG forming method.
FIGS. 1A-1C are flow diagrams which show process steps of a prior art technique for forming HSG selectively on the surface of the conductive layer pattern of the capacitor in a reacting chamber.
The method comprises the steps of filling in a contact hole formed in an oxide layer 12 formed on a semiconductor substrate 10 with silicon to form the conductive layer pattern of the capacitor 14 (FIG. 1A), introducing a reacting or source gas into the reacting chamber to form HSG nuclei 16 on the surface of the conductive layer pattern 14 (FIG. 1B), and growing the HSG nuclei 16 to form an HSG layer 16a (FIG. 1C).
The selective HSG forming process is generally performed in a cold or warm wall type reacting chamber since a selectivity loss margin (the undesirable lateral encroachment of HSG formation into an area outside of the patterned area) is the lowest.
In a cold wall type reacting chamber, an internal wall of the chamber is maintained at a temperature of about 10° C. to 20° C. by flowing cooling water along an internal wall to prevent any reacting gas from depositing any particulate on the inner surface of the internal wall. A warm wall type reacting chamber is comprised of a quartz wall surrounding a silicon carbide susceptor, and may be at a temperature between 200° C. to 500° C. The source gas introduced into the reacting chamber is typically pre-heated.
FIG. 2 is a graph which illustrates the relationship between an internal temperature and time in a reacting chamber in the prior art method of forming an HSG layer on the conductive layer pattern of the lower capacitor electrode in a cold wall type reacting chamber. Referring to FIG. 2, the method is divided into two steps, each step being performed at a distinct period of time. A first step stabilizes the temperature during a processing time (or interval) T1 and a second step forms the HSG. During a first time interval T1, the source gas is introduced into the reacting chamber to grow HSG on conductive layer patterns on the substrate. Once the internal temperature of the chamber has settled, the HSG layer is formed during a time interval T2.
Although the cold wall type reacting chamber approach will form a relatively large HSG nuclei, the amount of time which is required to fabricate the HSG layer results in a relatively longer processing time compared to the warm wall type reacting chamber. A longer processing period results in lower productivity and an increase in semiconductor production costs.
FIG. 3 is a graph illustrating a relationship between temperature and time in a warm wall type reacting chamber in the prior art method of fabricating the HSG layer on a surface of the lower capacitor electrode.
Referring to FIG. 3, the method for fabricating HSG by utilizing the warm wall type reacting chamber is divided into two steps: a first step T1′ involves stabilizing the temperature of the ambient and a second step T2′ involves forming and growing HSG nuclei. In the step of stabilizing temperature T1′, as illustrated in FIG. 3, the source gas is not initially introduced into the reacting chamber. After a temperature of the reacting chamber ambient is equal to that of the substrate and subsequently stabilized, the source gas is introduced into the reacting chamber T2′ to form the HSG nuclei and grow the HSG nuclei into an HSG layer by annealing.
Because the wall of the warm wall type reacting chamber may be at a temperature in the range of 200° C. to 500° C., the reaction time is shorter since the source gas is heated in the reacting chamber. However, the average grain size of the HSG layer tends to be smaller than that of the HSG layer formed in the cold wall type reacting chamber. The difference in grain size has a tremendous impact on the capacitance of the resulting capacitor. The smaller grain size formed using a warm wall type reacting chamber approach may cause the capacitance to be 10% to 20% lower than in the capacitor electrode formed in the cold wall type reacting chamber.
As a result, there exists a need for a method of fabricating a capacitor electrode with a relatively large surface area in order to increase capacitance in a relatively fast processing time to minimize production costs. Accordingly, an object of the present invention is to provide a method for fabricating a capacitor having relatively higher capacitance by enlarging an average grain size of an HSG layer formed on the lower capacitor electrode of the capacitor while not increasing the processing time and thus maintaining a low cost.